Add-On Lecture for Understanding the VLSI Design Flow

The Department of Electronics Engineering (VLSI Design and Technology) will conduct an add-on lecture titled “Understanding the VLSI Design Flow: From RTL to GDS” on 19^th September 2025.

This lecture will be delivered by distinguished speaker, Mr. Vikas Kalkeri, Principal Design Engineer, NXP Semiconductors. The session will delve into the fundamentals of Register Transfer Level (RTL) design, synthesis techniques, logic optimisation, and technology mapping, followed by an exploration of physical design steps such as floor planning, placement, routing, and timing analysis. Participants will also gain insights into verification strategies and the final tape-out process, culminating in GDSII file generation.