Two-Day Short Term Training Programme (STTP) on “Digital System Design using Altera FPGA”

The Department of Electronics and Communication Engineering is organising a Two-Day Short Term Training Programme (STTP) on “Digital System Design using Altera FPGA” on 26th and 27th September 2025. This hands-on training will cover key topics such as FPGA fundamentals, Quartus Prime design software, embedded system design, IP cores, and system integration using Platform Designer. The sessions will be led by Mr. Padmanaban Kalyanaraman, Software Enabling and Optimisation Engineer – CEG, Intel (Altera), who brings deep industry expertise and practical insights into FPGA-based system design.