The department of Electronics and Communication Engineering conducted a two-day STTP titled Digital System Design using Altera FPGA” on date in 26-09- 2025 to 27-09-2025 at 10.30 am, in Seminar hall 4.
The inaugural day of the Short-Term Training Programme (STTP) on “Digital System Design using Altera FPGA”, organised by the Department of Electronics and Communication Engineering, MVJ College of Engineering, was held on September 26, 2025, with enthusiastic participation from around 61 registered students. The event commenced at 10:30 AM with a warm welcome address by Dr. Shima Ramesh Maniyath, Head of the ECE Department, who also felicitated the resource person, Mr. Padmanaban Kalyanaraman, Software Enabling and Optimisation Engineer at Intel, CEG. The session began with an insightful overview of FPGA technology, its architecture, and its diverse applications in various industries, including automotive, broadcast, entertainment, instrumentation, and networking.