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The Analog Integrated Circuit Design Laboratory focuses on the design, simulation, and layout of fundamental analog building blocks using Cadence. Students gain practical experience in designing CMOS circuits such as inverters, amplifiers, differential pairs, and current mirrors through techniques like transistor sizing, biasing, and AC/DC analysis. The lab emphasises schematic design, layout generation, and post-layout simulation to evaluate key performance metrics such as gain, bandwidth, and delay. It enhances students’ understanding of analog design principles while developing proficiency in tools essential for modern analog and mixed-signal VLSI design.
The Digital System Design Using FPGA Laboratory provides hands-on training in designing, simulating, and implementing digital systems using Field Programmable Gate Arrays (FPGAs). Students learn to develop RTL code using Verilog or VHDL, synthesise digital circuits, and deploy them on FPGA development boards. The lab focuses on designing finite state machines, arithmetic units, memory controllers, and interface logic for real-time applications. With the help of industry-standard tools like Xilinx Vivado, students gain practical skills in timing analysis, constraint handling, and hardware debugging. This lab bridges theoretical digital design with real-world FPGA implementation, preparing students for advanced roles in embedded and hardware design.
The System Verilog for Verification Laboratory equips students with essential skills in functional verification of digital designs using SystemVerilog and industry-standard EDA tools such as Cadence. The lab emphasises building structured testbenches, writing constrained-random test scenarios, and developing assertion-based verification techniques. Through real-time simulation and debugging of RTL designs, the lab prepares students to tackle complex verification challenges, aligning their expertise with current VLSI industry practices.
The Digital VLSI Design Laboratory is a dedicated environment for the design, simulation, synthesis, and physical implementation of digital integrated circuits. Equipped with industry-standard tools such as Cadence, the lab enables students to work on RTL coding, logic synthesis and timing analysis. Students gain hands-on experience with the complete digital design flow, from behavioural modelling to gate-level verification and post-layout simulations. This lab fosters a deep understanding of digital circuit optimisation, area and power trade-offs, and real-world design constraints, preparing students for professional roles in digital IC and SoC design.
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MVJ College of Engineering, Near ITPB, Whitefield, Bangalore-560 067